Design Option Analysis of SRAM-based FPGAs in Safety-Critical Systems  
Author Xiangfen Wang
Co-Author(s) Yiliu Liu; Mary Ann Lundteigen; Cheng Gao; Jiaoying Huang
Abstract SRAM-based FPGAs are increasingly used in safety-critical systems. However, with the feature size shrinks to the nanometer scale, SRAM-based FPGAs become vulnerable to soft errors such as single-event upset. International standard IEC61508 (2010) introduces the aspects such as on-chip redundancy in detail and can thereby be taken into consideration by designers at early design stage. Triplicated modular redundant structures are common accepted by designers as two out of three on-chip redundancy solutions. This paper adopts the PDS method to calculate the average frequency of dangerous failures per hour of different triplicated modular redundancy structures of SRMA-based FPGAs. Influences of different factors are analyzed, to determine the corresponding safety integrity level. Results show that the use of two out three on-chip redundancy can effectively improve the safety integrity level. In addition common cause failures are the main restriction of on-chip redundant systems when chip failure rate decreases. Triplicated modular redundancy with partitions and diversity can improve reliability by decreasing the common cause failure.
Keywords Reliability analysis, Design Option, SRAM-based FPGA, Safety-critical system
   
    Article #:  23-190
 
Proceedings of the 23rd ISSAT International Conference on Reliability and Quality in Design
August 3-5, 2017 - Chicago, Illinois, U.S.A.