A Mechanistic Model for Microprocessor Architectural Vulnerability Factor Based on Constraints of Parallelism  
Author Liu Tang

 
Co-Author(s) Zhangqin Huang

 
Abstract Architectural Vulnerability Factor (AVF) is an important metric to evaluate microprocessor reliability. Mechanistic methods for modeling AVF may reveal how program and micro-architecture influence AVF. Based on the constraints of program parallelism and machine parallelism for a superscalar out-of-order processor, we propose a mechanistic model with mathematical descriptions for instruction flow, and infer the AVF formulas by modeling instruction occupancy. Comparing with prior mechanistic models, the key novelty of this model is that it expands more mechanisms that hardware and software parameters correlate with AVF. This provides sufficient quantitative analysis of the relationships between parameters and AVF. We demonstrate that the model can be used to perform reliability-aware design space exploration instantaneously.

 
Keywords reliability, microarchitecture, architectural vulnerability factor, mechanistic model, soft error rate
   
    Article #:  22317
 
Proceedings of the 22nd ISSAT International Conference on Reliability and Quality in Design
August 4-6, 2016 - Los Angeles, California, U.S.A.